Speaker
Description
Implementing digital signal processing (DSP) solutions on FPGAs is a challenging task that requires technical knowledge of the system and the functionality of algorithms. Using High-Level Synthesis (HLS) tools for handling DSP tasks accelerates the implementation process and reduces the development stage. Moreover, HLS solutions decrease FPGA verification time and provide flexibility for configuring design parameters with extensive iteration capabilities. In this paper, hardware accelerator units are introduced to correct the driven Radio Frequency (RF) signals in Low-Level RF (LLRF) multi-cavity controller systems. In RF stations, a portion of the injected signal into cavities is reflected due to the mismatch in the frequency of the forward signal and the resonance frequency of cavities. The presented design improves the forward signal in multi-cavity stations by real-time removal of the cross-coupling effect from the signal. This is achieved using the concepts of pipelining, parallelism, and the proper usage of FPGA resources for DSP calculation. Moreover, the paper introduces a real-time monitoring system for RF systems. Proposed units are used for detecting anomalies in the system by comparing the actual probe signal from each station with the virtual probe calculated based on the input signal. The main benefits of this solution are real-time calculation of corrected signals using DSP techniques and the introduction of an anomaly detector. Furthermore, this design reduces the workload from other parts of the system with off-load correction and monitoring of the RF cavities, leading to better performance of the overall system.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |
