Speaker
Description
This contribution explores the feasibility of using high-level C/C++ like languages to achieve the integration of specilied FPGAs-based applications with the function blocks of the ITER Real-Time Framework (RTF). RTF enables the development, deployment and execution of instrumentation and control (I&C) applications optimized for real-time performance on ITER CODAC Core System. High Level Synthesis (HLS) and OpenCL are high-level synthesis languages that allow users to implement complex algorithms on FPGA deevices using C/C++ programs. From this perspective, using FPGAs allows to increase the computational power limiting the latencies of a specilied functional block that is run in RTF. The proposal presented notably reduces development time and maintenability compared to the solutions based on Hadware Description Languages, such as VHDL or Verilog.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | Yes |
