25–29 May 2026
La Biodola - Isola d'Elba (Italy)
Europe/Rome timezone
Reminder: Posters are requested to be uploaded by Thursday, 21 May.

Fast Beam Position Calculation Implemented in FPGA

26 May 2026, 18:30
20m
Maria Luisa Room (Hotel Hermitage)

Maria Luisa Room

Hotel Hermitage

Oral presentation Real Time Diagnostics, Digital Twin, Control, Monitoring, Safety and Security Data Acquisition and Trigger Architectures

Speaker

Mr Wei Peng (Anhui University)

Description

This paper presents the design of electron beam position processor with a fast beam position calculation implemented in FPGA. The beam position processor will be adopted to the free electron laser and high magnetic field (FEL-HMF) facility constructed by Anhui University in Hefei, China. The beam position processor consists of a RF front-end board, an ADC and FPGA board and an AC/DC power supply module, which is able to process 476 MHz RF signal from beam position pick-ups in sampling rate of 250 Msps. The RF front-end board cascading two low-pass filters, two bandpass filters, two low-noise amplifiers and a digital attenuator, achieving performances of out-of-band suppression >60 dB across the 466–495 MHz frequency range. Its total gain is 40 dB and controllable gain is 31 dB with 1 dB step. The ADC and FPGA board have two dual-channel ADC chips and an Zynq SoC XC7Z045. We have implemented all digital signal process and data calculation in FPGA to reduce latency and enhance throughout. We test the beam position processor and compare the results of x and y with CPU calculation. The results show that the total processing latency is less than 100 sampling clocks, the position precision STD for x-axis direction is 8.8 μm and for y-axis direction is 1.4 μm, and the differences between CPU and FPGA are 1.3 μm and 0.52 μm.

Minioral Yes
IEEE Member No
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Author

Mr Wei Peng (Anhui University)

Presentation materials

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