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Description
Silicon photomultipliers (SiPMs) are widely recognized for their exceptional light response and high gain characteristics. Nonetheless, their practicality in fast timing applications is often impeded by their substantial terminal capacitance, which commonly exceeds 300 pF. To address this challenge, this study introduces a novel front-end readout electronics design. This architecture comprises a two-stage common-base transimpedance preamplifier and a 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analog-to-digital-converter (ADC). Through extensive SPICE simulations, utilizing the Hamamatsu S13360-6025 as the input source, the preamplifier circuit achieves a rise time of 700 ps and exhibits exceptional linearity. Meanwhile, experimental results from laser testing showcase that the proposed fast preamplifier design achieves a remarkable single-channel time resolution performance of better than 20 ps. As for the ADC circuit, considering the TSMC65nmLP process capability, a two-stage pipelined SAR structure is adopted, incorporating a two-step conversion technique (6-bit + 7-bit), with the second step employing redundancy design to reduce Vref buffer requirements. Experimental testing conducted at a sampling rate of 160M and an input condition of 80M reveals that, for Vpk = -1dBFS, the FFT spectrum analysis of the ADC demonstrates an effective number of bits (ENOB) of 9.34 and a spurious-free dynamic range (SFDR) of 73.8 dBc. Ongoing experiments are being systematically conducted, involving the connection of the fast preamplifier with the ADC, while future research endeavors encompass comprehensive investigations incorporating detectors to evaluate timing resolution in a holistic manner.
| Minioral | Yes |
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| IEEE Member | No |
| Are you a student? | Yes |
