Speaker
Description
Silicon photomultiplier (SiPM) was increasingly applied in nuclear medicine imaging development in recent years, especially in positron emission tomography (PET) scanner. To achieve a cost-effective, power-efficient signal processing unit for the SiPM array, a compact 128-channel front-end electronic (FEE) system based on dual-polarity charge-to-digital converter (dQDC) was proposed. A dQTC circuit consists of two resistors, a commercial amplifier, an integration capacitor, a voltage-referenced receiver and a discharging I/O pin in the FPGA. The hardware of the 128-channel FEE consists of an analog board and an FPGA board. In the analog board, 128 channels of dQDC analog circuits are implemented. The FPGA board is based on a low-cost FPGA, instantiating 128 LVDS receivers that serve as 128 voltage comparators. The SSTLⅡ standard is used to maximize the dynamic range of the dQTC circuit. The electronics performance of the FEE is evaluated in terms of noise, linearity, and uniformity. A PET detector is used to verify the readout capability of the 128-channel FEE system. The PET detector is made up of a 15×15 lutetium-yttrium oxyorthosilicate (LYSO) array and two SiPMs. The LYSO array is coupled with the two SiPM array at two ends. With the 128-channel FEE, the energy resolution (ER) of the PET detector is about 13.2%, and Peak-to-Valley Ratio (PVR) is 6.02. Currently, a time-to-digital converter is being developed to achieve a high-precision timing measurement for the PET detector. All the results of the performance evaluations including electronics and detectors will be presented in the meeting.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | Yes |
