Speaker
Description
We present a new ADC/Data Processing Module, designed for Step 2 of the KOTO Experiment at J-Parc, Japan. Occupying 18 VME Crates, the current KOTO Step 1 readout system includes three distinctive blocks: the CsI calorimeter readout with 2,600 channels using custom 16-Channel, 14-Bit, 125MHz modules; the veto detector readout with 500 channels and the same type of ADC modules; and the beam hole veto detector readout with 100 channels and custom 4-Channel, 12-Bit, 500MHz ADC modules. Our new 16-Channel, 14-Bit, 500MHz ADC/Data Processing Module with the same 6U VME64 form factor and power requirements as the above mentioned 14-Bit, 125MHz modules, is designed for replacement. A powerful Intel Arria V FPGA is used for real-time triggering with clustering and total energy calculations, data pipelining and data packing. Two QSFP+ optical links will allow for data transfer rates up to 40Gbps per QSFP+ transceiver. Board configuration can be done either via a front panel SFP link or Ethernet port, while an auxiliary RJ45 connector with 4 LVDS lines can be used for system clock synchronization and triggering. The VME64 backplane provides an alternative path for configuration and low-rate data readout, but it is mostly used for initial testing and debugging. The module design will be described, and preliminary test results will be reported.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |
