Speaker
Description
High-speed data processing in DAQ using hardware accelerators such as GPU and FPGA has been gaining attention to accommodate the increasing intensity of accelerator beams. We have been investigating the possibility of implementing such hardware accelerator devices for the DAQ system at RIKEN RIBF. Alveo U50 is one of the series of data center accelerator cards provided by Xilinx, which contains an AMD Ultrascale+ FPGA chip with 8GB HBM (high-bandwidth memory). The board supports PCI Express for installation in typical workstations or computing servers, as well as 100Gbps connectivity with a QSFP28 port. Using the Alveo U50, we have implemented the particle identification algorithm for the BigRIPS fragment separator and succeeded in reproducing the results obtained with the typical offline analysis software. In particular, the data processing throughput exceeds that of CPU, even though the C++ codes are automatically converted to RTL by high-level synthesis without any manual tuning of the RTL design. We see potential in this scheme and are exploring the possibility of further applications. In this contribution, we will present the current status of this project and future prospects.
| Minioral | No |
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| IEEE Member | No |
| Are you a student? | No |
