24th IEEE Real Time Conference - ICISE, Quy Nhon, Vietnam

Session

Oral presentations

Day 2 - Afternoon

23 Apr 2024, 13:50

143. Reconstruction of pile-up events using an Autoencoder based on CNN for the NEDA detector array.

Jose Manuel Deltoro Berrio (Universitat de Valencia)

23/04/2024, 13:50

AI, Machine Learning, Real Time Simulation, Intelligent Signal Processing

Oral presentation

Pulse pile-up poses an issue in the study of nuclear reactions and spectroscopy, arising when two pulses overlap, distorting data and compromising the accuracy of energy and timing details. Various digital and analogue techniques have been used to deal with pile-up interference. However, some pile-up events may include interesting pulses that require reconstruction.
This study introduces a...

176. Machine Learning for Sub-Microsecond Edge Data Processing

Prof. Audrey Corbeil Therrien (Université de Sherbrooke)

23/04/2024, 14:10

AI, Machine Learning, Real Time Simulation, Intelligent Signal Processing

Oral presentation

The improvements in artificial intelligence, particularly the many flavours of Machine Learning (ML), add a powerful and versatile tool to data acquisition (DAQ) strategies. However, large and deep neural networks remain memory and compute intensive, limiting their usability at the edge. One of the most important aspect of integrating ML in a DAQ system is determining when and where...

135. A QGP Trigger for the CBM Experiment based on Artificial Neural Networks

Prof. Ivan Kisel (Uni-Frankfurt, FIAS, GSI, HFHF)

23/04/2024, 14:30

AI, Machine Learning, Real Time Simulation, Intelligent Signal Processing

Oral presentation

The field of heavy-ion experiments, such as the future Compressed Baryonic Matter (CBM) experiment at FAIR, necessitates algorithms that are high in performance and efficient in real-time data analysis. The increasing integration of machine learning techniques, particularly artificial neural networks, into physics experiments marks a significant advancement in this domain. The report...

164. hls4ml: low latency neural network inference on FPGAs

Vladimir Loncar (Massachusetts Inst. of Technology (US))

23/04/2024, 14:50

AI, Machine Learning, Real Time Simulation, Intelligent Signal Processing

Oral presentation

Machine learning is becoming increasingly prevalent in High Energy Physics (HEP), offering significant potential for enhancing trigger and Data Acquisition (DAQ) performance, as well as other real-time control applications. However, the exploration of these techniques in low latency/power Field-Programmable Gate Arrays (FPGAs) is still in its early stages. We introduce hls4ml, a user-friendly...

171. Development of ML FPGA filter for particle identification and tracking in real time

Sergey Furletov (Jefferson Lab, (US))

23/04/2024, 15:10

AI, Machine Learning, Real Time Simulation, Intelligent Signal Processing

Oral presentation

With the increase of luminosity for accelerator colliders as well as a granularity of detectors for particle physics,
more challenges fall on the readout system and data transfer from detector front-end to computer farm and long term storage.
Modern concepts of trigger-less readout and data streaming will produce large data volumes being read from the detectors.
From a resource standpoint,...

48. High-speed data processing in the RIBF DAQ system using the Alveo data-center accelerator card

Yuto Ichinohe

23/04/2024, 16:00

Data Acquisition and Trigger Architectures

Oral presentation

High-speed data processing in DAQ using hardware accelerators such as GPU and FPGA has been gaining attention to accommodate the increasing intensity of accelerator beams. We have been investigating the possibility of implementing such hardware accelerator devices for the DAQ system at RIKEN RIBF. Alveo U50 is one of the series of data center accelerator cards provided by Xilinx, which...

68. Readout system for a strip ionization chamber dedicated for proton beam profile measurement

Ye Lin (Shanghai Advanced Research Institute, CAS)

23/04/2024, 16:20

Data Acquisition and Trigger Architectures

Oral presentation

This work presents a 448-channel readout system integrated into a multi-strip ionization chamber for proton beam profile measurements. Miniaturized current-input ADCs inside the detector vessel provide direct digitization of charge collected on 1.5mm cathode strips. An FPGA configures ADCs dynamically and handles acquisition triggering and data processing, enabling real-time beam analysis....

109. DAQ system for CEPC Vertex detector prototype

Chang Xu

23/04/2024, 16:40

Data Acquisition and Trigger Architectures

Oral presentation

Abstract: The discovery of the Higgs boson was a significant milestone in the history of particle physics. In pursuit of more precise measurement of the Higgs boson’s properties and interactions, Chinese high-energy physicists proposed the Circular Electron Positron Collider (CEPC) project. The silicon pixel vertex detector, which requires high spatial resolution, low material budget, and...

173. FERS-5200: a distributed Front-End Readout System for multidetector arrays

Dr Carlo Tintori (CAEN SpA)

23/04/2024, 17:00

Industry and Industry collaboration

Oral presentation

The FERS-5200 is the new CAEN Front-End Readout System, answering the challenging requirement to provide flexibility and cost-effectiveness in the readout of huge detector arrays. FERS-5200 is a distributed and easy-deployable platform integrating the whole readout chain of the experiment, from detector front-end to DAQ. It is based on compact ASIC-based front-end cards integrating A/D...

63. Simplified Firmware Development for Open FPGA Platforms in DAQ Systems using SciCompiler

Andrea Abba (Nuclear Instruments SRL)

23/04/2024, 17:20

Emerging Technologies, New Standards, Feedback on Experience

Oral presentation

In the realm of modern trigger and data acquisition (DAQ) systems, the adoption of programmable logic devices underscores the advantages of versatile, reusable mixed-signal platforms, known as open FPGA boards. These boards enable seamless integration of custom processing algorithms into firmware, enhancing their appeal across diverse applications. However, FPGA development languages like VHDL...