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This paper presents the design and test results of a 2.56Gbps deserializer with a full-rate clock and data recovery (CDR) fabricated in a 55nm CMOS process for applications in high-energy physics experiments.The PLL-based CDR recovers the 2.56GHz clock from the input data and retiming the data.Then the 2.56Gbps retimed data and the 2.56GHz recovered clock are used as the input for the deserializer.The 1:16 deserializer mainly includes a 1:4DEMUX module and a 4:16DEMUX module consisting of 1:4DEMUX units and two divider-by-4, which completes the conversion from a 2.56Gbps serial data to 16 channels 160 Mbps/Ch parallel data.The 1:4DEMUX unit in deserializer is implemented by orthogonal clock sampling, which reduces the requirement of clock frequency and increases the sampling margin.And the LC-VCO in CDR uses a capacitor array with high Q value to realize frequency fine tuning and optimize phase noise.The 2.56Gbps deserializer and the full-rate CDR are integrated in a large chip that has been taped out and fully tested. The test results show that the RMS jitter of the 2.56GHz recovered clock from CDR is 859.71fs with a phase noise of -110dB@1MHz. The total jitter (TJ) of the retimed 2.56Gbps data, which is output from the chip by a CML driver for test, is 32.54ps. And all the 16-channel outputs of the deserializer have been captured, saved and analyzed. Wide-open eyes have been captured, and the logic of 16-channel outputs of the deserializer has been verified. The detailed design and the test results will be presented in the paper.
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