Speaker
Description
In Japan, a community of users in experimental physics has been actively developing and deploying a generic streaming DAQ system. This system requires precise time synchronization among FPGAs in the front-end electronics and employs an original time-synchronization protocol implemented on FPGAs using general I/O pin pairs. Previously, the protocol was available only on AMD Kintex-7 FPGAs, which significantly limited the generality of the system. To address this limitation, we investigated differences between FPGA families and introduced two extensions.
First, the protocol was extended to operate on both the AMD 7-series and UltraScale FPGA families. The protocol utilizes the IDELAY and IOSERDES primitives; however, because different generations of these primitives are employed in the two families, their functionality and control schemes differ. To address this issue, we modified the surrounding circuitry of the primitives in the UltraScale family to achieve behavior equivalent to that of the AMD 7-series.
Second, differences in input signal delays introduced by the ISERDES and IDELAY primitives between two FPGAs were addressed, since accurately determining these differences is essential for precise time synchronization. Although these delay differences include device-specific components, they were previously neglected because communication was limited to identical devices. By explicitly determining the device-specific delays, the protocol was updated to enable time synchronization between different devices.
The updated time-synchronization system was implemented on various FPGA devices, and an accuracy within approximately 300 ps was achieved across all device combinations, confirming that the performance attained prior to the update was fully preserved.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |