Speaker
Description
LHCb, one of the four main experiments at CERN, was upgraded for Run 3 to enable fully software-based triggering and data acquisition. A key component of this upgrade is the Upstream Tracker (UT), a silicon microstrip detector installed in early 2023. The UT comprises 968 silicon sensors and approximately 4192 SALT ASICs, which perform analog processing, digitization, common-mode subtraction, zero suppression, and data serialization. The resulting data streams are transmitted to the TELL40 back-end readout boards.
Each TELL40 board can be viewed, in simplified terms, as a set of optical fibre receivers connected to a high-performance Intel Agilex 10 FPGA, responsible for data processing and transfer to a PCIe interface.
This contribution focuses on the TELL40 FPGA gateware developed for the UT readout. It describes the challenges posed by the UT electronics architecture, data formats, high data rates and zero deadtime. It presents the adopted mitigation strategies, which reduced system complexity at the cost of specific trade-offs.
In addition to the core data acquisition functionality, several monitoring and control mechanisms were implemented within the Experiment Control System (ECS) and the Timing and Fast Control (TFC) system. The resulting architecture and the key design decisions are presented.
Finally, the development of a system with custom inputs and outputs required the application of dedicated design verification and debugging techniques, as well as the development of supporting software, which are also described.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |