Speaker
Description
Radiation detection in medical imaging and high energy physics often requires precise time measurement to retrieve as much information as possible from the detected particles. Time-to-digital converters (TDCs) are a critical part of the acquisition chain to produce these measurements. FPGAs offer a flexible and cost-effective platform to implement tapped-delay-line (TDL) TDCs with precision and resolution in the picosecond order. These metrics have improved with each new FPGA generation, owing notably to improved fabrication processes with smaller delay and skew. This makes the newest architecture from AMD, the Versal architecture, a prime candidate for implementing TDL TDCs. Using the new configurable logic block and carry chain circuit, two different configurations of TDL TDC were implemented in the Versal architecture. Using a model based on signal delay and clock skew inside the TDL, the resolution and quantization error were estimated to be respectively 2.93 ps and 2.75 ps in the best configuration. This is worse than in previous architectures owing to less uniform clock skew and higher average delay caused by the new configurable logic block circuit.
| Minioral | Yes |
|---|---|
| IEEE Member | Yes |
| Are you a student? | No |