25–29 May 2026
La Biodola - Isola d'Elba (Italy)
Europe/Rome timezone
Reminder: Posters are requested to be uploaded by Thursday, 21 May.

GPU-Based Level-3 Real-Time Trigger for the Belle II High Level Trigger System

25 May 2026, 17:15
20m
Maria Luisa Room (Hotel Hermitage)

Maria Luisa Room

Hotel Hermitage

Oral presentation Data Acquisition and Trigger Architectures Data Acquisition and Trigger Architectures

Speaker

Prof. Ryosuke Itoh (KEK)

Description

The Belle II experiment at KEK is a next-generation B-factory designed to operate at unprecedented luminosity. During recent SuperKEKB operations, unexpectedly high background has led to a significant increase in the Level-1 trigger rate. If this situation persists as luminosity continues to improve, the processing capacity of the Belle II High Level Trigger (HLT) system may exceed its original design limits.

The current HLT is implemented as a large-scale PC farm equipped with ~7,200 Intel Xeon CPU cores. While this system provides sufficient processing power for physics events at the design luminosity, further expansion is not cost effective. In contrast, modern GPUs offer a substantially larger number of processing cores at a much lower cost per performance, making them attractive for real-time event rejection.

To address this challenge, we propose the introduction of a GPU-based processing stage in front of the existing HLT, implementing a software-based Level-3 trigger. This Level-3 trigger performs fast particle tracking and energy clustering using a limited detector set. Background events are efficiently identified by reconstructing the event origin and rejecting events inconsistent with the nominal beam collision region.

A uniform software development environment compatible with the Belle II framework is realized by integrating CUDA compilation into the existing SCons-based build system. GPU binaries are directly linked with the Belle II framework (basf2), enabling integration with existing C++ codes. The GPU system is implemented in the HLT input servers using NVIDIA RTX 5000 Ada GPUs. System design, data-flow architecture, and performance in beam tests are presented.

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Authors

Prof. Ryosuke Itoh (KEK) Seokhee Park (KEK) Jongkuk Min (Yonsei University)

Co-authors

Mikihiko Nakao (KEK) Satoru Yamada (KEK) Soh -Yamagata- Suzuki (KEK) Takuto Kunigo (KEK) Mikhail Remnev (KEK)

Presentation materials

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