Speaker
Description
In large-scale physical experiments, the multigigabit transceivers (MGTs) in field-programmable gate arrays (FPGAs) have become a prevalent choice to implement high-precision clock distribution and synchronization. However, the temperature-induced delay drift in MGTs and other electronic components has not been well investigated, posing a significant challenge to synchronization stability at picosecond levels. This paper first characterizes the temperature coefficients of MGTs in Xilinx Kintex UltraScale+ FPGA and then implements temperature compensation in a clock distribution and synchronization system to demonstrate performance enhancement. Utilizing an on-chip, temperature-robust Dual-Mixer Time Difference (DDMTD) method, the temperature coefficients in the transmitter (TX) and receiver (RX) are measured as 1.42 ps/°C and 0.59 ps/°C respectively. After applying compensation, within a temperature range from 35°C to 80°C, the maximum drift of the clock distribution is reduced from 90.7 ps to 7.6 ps. The significant temperature effect in the TX is theoretically analyzed at the end of this paper.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | Yes |