25–29 May 2026
La Biodola - Isola d'Elba (Italy)
Europe/Rome timezone
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Online Data Reduction for the ePIC dRICH Using a Multi-FPGA Neural Network

28 May 2026, 16:20
20m
Maria Luisa Room (Hotel Hermitage)

Maria Luisa Room

Hotel Hermitage

Oral presentation Data Acquisition and Trigger Architectures Data Acquisition and Trigger Architectures

Speaker

Cristian Rossi (INFN Sezione di Roma)

Description

The ePIC detector at the Electron-Ion Collider (EIC) includes a dual-radiator Ring Imaging Cherenkov sub-detector (dRICH) in its forward region providing particle identification capabilities over a wide momentum range. The system is partitioned into six sectors, each instrumented with ∼53k Silicon PhotoMultipliers (SiPMs) featuring single-photon sensitivity, and transmits hit data over ∼320k detector channels to the Data Acquisition (DAQ) system.
In the DAQ front-end, data from 4,992 Front-End Boards (FEBs)–each integrating an ALCOR64 ASIC to digitize signals from 64 SiPMs–are aggregated by 1,248 Readout Boards (RDOs) and transmitted via VTRx+ optical links to 30 back-end Data Aggregation and Manipulation Boards (DAMs). Each DAM–implemented with the FPGA-based FELIX-155 PCIe card from the ATLAS experiment–merges data from up to 42 RDOs and transfers them via PCIe to host memory, which then forwards event fragments to the experiment buffering system via 100 GbE.
During operation, radiation-induced damage is expected to increase the SiPM Dark Count Rate (DCR) to peaks of 300 kHz per channel. Given this high noise floor and the low percentage of bunch crossings producing physics events, the necessity of an online data reduction system classifying and filtering the DCR noise-only events in
the DAQ back-end to maintain its output data rate at a manageable level has emerged.
We present a design based on a local triggering scheme, where the trigger signal evaluation is performed by an online classifier implemented as an MLP-based neural network distributed over the multi-FPGA system composed of 30 DAMs plus a dedicated Trigger Processor (TP) card.

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Author

Cristian Rossi (INFN Sezione di Roma)

Co-authors

Alessandro Lonardo (Sapienza Universita e INFN, Roma I (IT)) Andrea Biagioni (INFN) Mr Andrea Ciardiello (INFN Sezione di Roma) Mr Evaristo Cisbani (INFN Sezione di Roma) Mrs Francesca Lo Cicero (INFN Sezione di Roma) Mr Francesco Simula (INFN Sezione di Roma) Luca Pontisso (Sapienza Universita e INFN, Roma I (IT)) Mr Ottorino Frezza (INFN Sezione di Roma) Piero Vicini (INFN Rome Section) Mr Pierpaolo Perticaroli (INFN Sezione di Roma) Mr Roberto Ammendola (INFN)

Presentation materials

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