25–29 May 2026
La Biodola - Isola d'Elba (Italy)
Europe/Rome timezone
NB: The submission deadline for the Student Paper Awards is Monday, 11 May.

Triggerless Data Acquisition for Online Reconstruction in High-Rate Experiments

28 May 2026, 17:30
20m
Maria Luisa Room (Hotel Hermitage)

Maria Luisa Room

Hotel Hermitage

Oral presentation Data Acquisition and Trigger Architectures Data Acquisition and Trigger Architectures

Speaker

Yifeng Wang (ETH Zurich (CH))

Description

Traditional triggerer DAQ performs explicit hardware rate control: only events passing a fast trigger are fully read out. This reduces throughput and buffering demands, but can lose physics because the decision uses partial detector information and a short time window, and it imposes pipeline buffering on the trigger-latency timescale.

Triggerless (free-running/streaming) DAQ streams all zero-suppressed hits and moves selection to an online reconstruction farm. The key constraint is in-order processing: the farm consumes fixed-width time slices strictly in chronological order, so the event-building network must output one globally time-ordered stream. Variable transport delay creates cross-lane skew; any late slice causes head-of-line blocking and reordering buffer growth, so strict ordering requires an order-preserving barrier that waits for the slowest lane. Thus, the choice and placement of sort/merge primitives directly determine system-wide total buffer size (which can be even unbounded) and sustainable throughput.

We review prior sorter/merger approaches and show why they do not scale to high-rate streaming. We then present a novel architecture: a cascading non-order-preserving merger$\rightarrow$sorter(resequencer) pipeline feeding a single final barrier. Under our scheme, locally bounding skew at each fan-in stage prevents system-wide accumulation, minimizes end-to-end buffering, and maximizes sustained throughput under realistic burstiness and transport variability.

Minioral Yes
IEEE Member Yes
Are you a student? Yes

Author

Yifeng Wang (ETH Zurich (CH))

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