Speaker
Description
Time-to-Digital Converters (TDCs) are indispensable components in data acquisition systems for particle and nuclear physics experiments. While performance requirements vary by detector, applications such as Multi-Wire Drift Chambers (MWDCs) and Parallel Plate Avalanche Counters (PPACs) demand high channel density with moderate resolution, ranging from 100 ps to 1 ns.
To address this, we have developed a cost-optimized TDC implemented on the AMD Artix-7, an affordable FPGA device. Although the multi-phase clocking technique is well-established, this design focuses on achieving high channel density and sufficient resolution by effectively utilizing the resources of the device. By employing manual routing to finely tune propagation delays between internal components, we successfully integrated 64 signal channels plus one trigger channel into a single chip.
Two firmware versions were developed: a 312.5 ps least significant bit (LSB) version supporting both leading and trailing edge detection, and a 125 ps LSB version for leading edges. The system features a trigger-matching mode to filter hits within a programmable coincidence window. This TDC has already been deployed in accelerator-based nuclear physics experiments, demonstrating stable operation. This contribution reports on the implementation strategy using manual routing, the achieved performance, and the practical advantages of using cost-efficient FPGA platforms for high-density TDC systems.
| Minioral | Yes |
|---|---|
| IEEE Member | Yes |
| Are you a student? | No |