Speaker
Description
Next-generation telescopes require front-end electronics able to sustain multi-gigabit data streams while preserving deterministic timing and reliable event delivery. A new evolution of the FADC (Fast Analog-to-Digital Converter) board, a digitizer board originally developed for the CTAO-LST Advanced Camera, is presented, extending it into a fully self-contained, network-attached front-end module.
The new board integrates two FPGAs: a high-performance data FPGA responsible for trigger, buffering and data acquisition, and a service FPGA dedicated to timing distribution, White Rabbit synchronization and slow control. High-rate waveform data are streamed directly from the front end to DAQ servers using a 10 GbE RoCEv2 RDMA engine written in Bluespec SystemVerilog and released as open-source, enabling zero-copy, low-latency transfers without CPU intervention.
To guarantee lossless and deterministic operation in a funneling network topology, a hardware implementation of DCQCN (Data Center Quantized Congestion Notification) is being developed and tightly coupled to the RoCEv2 engine. DCQCN dynamically regulates the RDMA injection rate by delaying packet emission toward the UDP/MAC layer in response to ECN feedback from the Ethernet fabric.
The algorithm has been optimized using an ns-3 simulation environment that reproduces realistic experiment network conditions, allowing extraction of stable and high-throughput control parameters prior to hardware deployment. The resulting firmware architecture provides an end-to-end congestion-aware RDMA data path directly at the detector front end.
This approach enables scalable, trigger-capable, and network-native readout electronics well suited for large-channel-count experiments and future real-time distributed DAQ systems.
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| IEEE Member | No |
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