25th IEEE Real Time Conference - La Biodola, Elba, Italy

Studies of FPGA accelerated track reconstruction for the ATLAS Event Filter

28 May 2026, 18:10

20m

Maria Luisa Room (Hotel Hermitage)

Oral presentation Data Acquisition and Trigger Architectures Data Acquisition and Trigger Architectures

Speaker

Kevin Sedlaczek (Northern Illinois University (US))

Description

The upcoming high-luminosity phase of the LHC (HL-LHC) presents several challenges for the ATLAS experiment's Trigger and Data Acquisition system, necessitating a full upgrade of the system. A key challenge for the Event Filter, where high-level event reconstruction and final event selection will run at 1 MHz, lies in the computational demand for online track reconstruction within the Inner Tracker. Over the past few years, extensive research has been conducted into utilising hardware accelerators in the ATLAS Event Filter system to improve tracking throughput and reduce full-system power consumption. Various end-to-end track reconstruction pipelines have been developed using GPUs and FPGAs. These pipelines demonstrate their capabilities by offloading different amounts of the computing load to the accelerators.

This contribution focuses on developments in FPGA-based track reconstruction pipelines integrated into the ATLAS software framework, Athena. A high-throughput FPGA accelerator for hit clustering and data preparation has been implemented in hardware, and various algorithmic extensions have been studied. The results will be compared with those of the CPU and GPU counterparts.