Speaker
Description
This paper presents the design, implementation, and verification of ITER's Central Interlock System Critical Gateway (CIS-CG), a system for real-time emergency pulse termination. The CIS-CG serves as the critical interface coordinating protective actions among the Plasma Control System (PCS), the Advanced Protection System (APS) and the Central Interlock System (CIS), during fault conditions.
The system implements a general solution that addresses the ITER investment protection goals through configuration, while enabling early integration with evolving plant designs. Its functional architecture includes 42 configurable stop-codes mapped to 32 composite interlock actions through a priority-based countdown mechanism. This design enables adaptable protection strategies through configuration rather than hardware modifications as operational requirements and risks evolve.
The dual-redundant architecture of the system operates with 100 µs control loop timing across the Main Server Room (MSR) and the Backup Server Room (BSR), utilizing CIS Fast Architecture FPGA-based technology. Operation of this interlock system bridges the gap between ITER's pulsed interlock operating states and ITER's Common Operating States (COS) that is responsible for orchestrating pulsed operation between the tokamak diverse plant systems. This system represents the first IEC61508 compliant implementation enabling critical parameter communication from the pulse-schedule to the interlock layer.
Test results demonstrate the system's capability to meet stringent reliability requirements while maintaining configurability and fail-safe operation throughout ITER's experimental campaigns.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |