Speakers
Dr
Chong Liu
(University of Science and Technology of China)Prof.
Yonggang Wang
(University of Science and Technology of China)
Description
The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.
Author
Dr
Chong Liu
(University of Science and Technology of China)
Co-authors
Dr
Deng Li
(University of Science and Technology of China)
Mr
Peng Kuang
(University of Science and Technology of China)
Dr
Xinyi Cheng
(University of Science and Technology of China)
Prof.
Yonggang Wang
(University of Science and Technology of China)
