Speakers
Description
Frontier physics explorations, such as the heavy-ion experiments at the High-Intensity heavy-ion Accelerator (HIAF) and NvDEx experiment at CJPL to search for neutrinoless double-beta decay, demand and thus propel the rapid development of new detector technologies. To address this demand, the next-generation multi-channel readout ASIC must integrate high-performance analog-to-digital converters as a core component. The ADC must deliver high precision and high speed to accurately capture signals, and operate within a tight power budget and a compact area to support high-density on-chip integration. In this paper, we have developed a novel 14-bit, 100 MS/s, pipelined SAR ADC in a 55 nm CMOS process. Two CDACs are used in stage-one's SAR ADC and MDAC to save power. Also, a novel MDAC structure that separates the CDAC from the amplifier inputs is adopted to improve the speed and gain error. The ADC added an extra reset phase to eliminate the memory effect of the CDAC in the stage-two SAR ADC. This paper will present the design and performance of this ADC.
| Minioral | Yes |
|---|---|
| IEEE Member | Yes |
| Are you a student? | No |