Speaker
Description
In nuclear and particle physics experiments, high-precision time measurement is a core technology for applications such as Time-of-Flight (TOF). Fast detectors, represented by Multi-gap Resistive Plate Chambers (MRPCs), are widely used in large-scale and high-resolution detector systems due to their excellent timing performance. However, their weak and fast output signals, combined with the integration limitations of traditional architectures that separate the analog front-end from digital quantization, pose severe challenges to readout electronics. To address this, an 8-channel high-precision time measurement ASIC, featuring monolithic integration of the analog front-end and digital back-end, was designed and implemented in a 180 nm CMOS process. The chip integrates pre-amplifiers, discriminators, Time-to-Digital Converters (TDCs), and a Phase-Locked Loop (PLL). The pre-amplifier employs a Regulated Cascode (RGC) topology to achieve both high bandwidth and low noise, while providing a stable and low input impedance for matching with various readout applications. The discriminator utilizes a differential saturated amplification structure, featuring low noise and low jitter. The TDC is based on a two-step vernier architecture, effectively balancing timing resolution, power consumption, and dead time. Furthermore, an on-chip low-jitter PLL based on a Multiplying Delay-Locked Loop (MDLL) provides a high-stability reference clock for the TDC. Test results from the fabricated chip show a stable input impedance as low as 15 Ω and a timing precision of 10 ps with a 100 fC input charge, validating the capability of the proposed monolithic solution for high-precision readout.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | Yes |