Speaker
Description
With the growing demand for real-time particle detection and precise event reconstruction, pixel detector readout chips with accurate timing capability for time-resolved particle tracking have become increasingly important. This work presents an energy- and timing-oriented pixel detector ASIC for three-dimensional particle track reconstruction.
The chip is fabricated in a GSMC 130~nm CMOS process and implements a $10 \times 10$ pixel array, occupying a total chip area of $1~\mathrm{mm} \times 1.5~\mathrm{mm}$, with each pixel measuring $90~\mu\mathrm{m} \times 50~\mu\mathrm{m}$. Two on-chip delay chains form the basis of the time measurement scheme, in which three selectable delay stages provide nominal delays of 812~ps, 7.18~ns, and 14.36~ns, respectively, achieving an intrinsic timing resolution of 278.4~ps. Each pixel integrates an analog front-end circuit composed of a low-noise charge-sensitive amplifier, a comparator, and a tunable delay module. The analog front-end achieves an equivalent noise charge of 13.9~$e^{-}$ and a charge-to-voltage conversion gain of 30.5~$\mu\mathrm{V}/e^{-}$. A digital readout circuit implements row--column rolling-shutter scanning across the pixel array.
Energy information is digitized by an external ADC, while timing information from on-chip tapped delay-chain outputs is processed in an FPGA to extract time-of-arrival values. The FPGA-processed data are transferred to a host computer for three-dimensional particle track reconstruction. Simulation results based on the proposed architecture demonstrate the feasibility of time-resolved three-dimensional particle tracking.
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