Speaker
Description
The upcoming high-luminosity phase of the LHC (HL-LHC) presents several challenges for the ATLAS experiment's Trigger and Data Acquisition system, necessitating a full upgrade of the system. A key challenge for the Event Filter, where high-level event reconstruction and final event selection will run at 1 MHz, lies in the computational demand for online track reconstruction within the Inner Tracker in selected regions of interest at the full trigger rate and of the full tracker acceptance at 150 kHz. Over the past few years, extensive research has been conducted into utilising hardware accelerators in the ATLAS Event Filter system to improve tracking throughput and reduce full-system power consumption. Various end-to-end track reconstruction pipelines have been developed using GPUs and FPGAs. These pipelines demonstrate their capabilities by offloading different amounts of the computing load to the accelerators.
This contribution focuses on developments and optimizations for GPU-based track reconstruction in regions of interest. The scaling of throughput and latency with the size and occupancy of regions of interest has been studied for GPU-based tracking pipelines originally designed for efficiently reconstructing full tracker acceptance simultaneously. Different approaches for improving the utilization of the GPU resources for the smaller regions are presented and compared to the full acceptance algorithms as well as the CPU counterparts.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |