Speaker
Description
The High-Luminosity Large Hadron Collider (HL-LHC) will deliver a five- to seven-fold increase in instantaneous luminosity relative to the original LHC design, and approximately a three-fold increase compared to Run-3 operation, significantly increasing detector readout volumes and placing substantially higher demands on the trigger and data-acquisition systems. To meet these challenges, the ATLAS Event Filter Tracking group is evaluating heterogeneous computing platforms to reduce the size, cost, and power consumption of the event-processing farm. Options where key algorithms of the processing are offloaded to either FPGA or GPU accelerator cards are compared directly to a traditional CPU-only farm. This contribution presents an FPGA-based implementation of the pattern-recognition stage in the tracking pipeline, developed using High-Level Synthesis and integrated within the ATLAS Athena software framework using the OpenCL cross-platform programming model. We describe the architecture, firmware design choices, and workflow for hardware-software co-execution. Performance studies compare physics efficiency and throughput of FPGA implementation against other technologies, demonstrating the potential of FPGA acceleration for the HL-LHC Event Filter.
| Minioral | No |
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| IEEE Member | No |
| Are you a student? | No |