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Description
The front-end electronics in the Far Detector of the Hyper-Kamiokande experiment are undergoing an upgrade in performance and complexity in comparison to its predecessor Super-Kamiokande. The electronics that read out the PMTs (20,000 Hamamatsu R12860) must be mounted inside sealed steel vessels in water. The inability to service the modules after installation, together with the need for more complex electronics, requires the development of a new board that will aggregate the data coming from the digitizer boards and transmit them through optical links to the DAQ, sitting outside the detector. Furthermore, this board must have high reliability to meet a maximum of 10% of failing units after 20 years of operation. Through a careful selection of components together with redundant elements, the target reliability is reached. This work describes the hardware design of the Data Processing Board (DPB), a System on Chip design that leverages a SOM-baseboard (Sytem On Module) layout that combines the versatility of the FPGAs with the power of CPUs, allowing both data taking and system monitoring for each of the one thousand vessels present in the Hyper-Kamiokande Far Detector. This design has already been tested and iterated upon by manufacturing pre-series units and is entering into mass production of one thousand units.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | Yes |