Speaker
Description
Commissioning of the detectors for the High‑Luminosity Large Hadron Collider (HL‑LHC), also referred to as the Phase‑2 upgrade, is planned for the period 2026–2028 at CERN. In this framework, the readout and control electronics of the Drift Tube (DT) subdetector of the CMS experiment have undergone a complete redesign. This upgrade is being carried out to cope with the expected increase in event rates and to ensure compatibility with the upcoming Trigger and Timing Control Distribution System (TCDS2). In parallel with this, a new back‑end system for timing distribution and slow control has been developed. This system is based on a set of FPGA‑based Advanced Telecommunications Computing Architecture (ATCA) boards onto which custom firmware has been deployed. Each board is connected to the server through a network interface and provides approximately one hundred high‑speed optical links implementing the Low Power Gigabit Transceiver (LpGBT) protocol, used to distribute machine‑synchronous timing signals and slow‑control commands to the detector electronics. The VHDL firmware integrates intellectual property (IP) cores, makes use of the SLAC Ultimate RTL Framework (SURF), and incorporates dedicated modules specifically designed to interface and manage custom on‑detector electronics. Moreover, a Python software library has been developed to configure, monitor, and control the boards through a dedicated Reliable User Datagram Protocol (RUDP) connection between the boards and the server.
This contribution will describe the overall design of the system, detail the implementation at the firmware level, and present the results of the benchtop and in‑field tests performed to date.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |