25–29 May 2026
La Biodola - Isola d'Elba (Italy)
Europe/Rome timezone
Reminder: Posters are requested to be uploaded by Thursday, 21 May.

FPGA-Based Multi-Channel Real-Time Readout System for the STCF Muon Detector Prototype

25 May 2026, 14:45
1h
Elena Room (Hotel Hermitage)

Elena Room

Hotel Hermitage

Poster presentation Front-End Electronics, Fast Digitizers, Fast Transfer Links & Networks Front-End Electronics, Fast Digitizers, Fast Transfer Links & Networks - PS

Speakers

Ms Qian He (Shandong University)Mr Hao Dong (Qufu Normal University)Mr Bo Wang (Shandong University)Ms Xiaohan Sun (Shandong University) Feng LI (USTC) Kun Hu (Shandong University (CN))Ms Yuying Li (Shandong University)

Description

The Super Tau-Charm Facility (STCF) is a proposed next-generation high-luminosity e+e- collider in China, operating at 2–7 GeV with a peak luminosity of about 0.5 × 10³⁵ cm⁻² s⁻¹. Its muon detector (MUD), located at the outermost layer of the spectrometer, must provide high muon detection efficiency while suppressing charged-hadron backgrounds. Since the hit position is encoded by the channel number, the readout electronics mainly need to record the arrival time of signals above a particle-identification threshold. For the prototype of the muon detector, we have therefore developed a multi-channel real-time readout system for precise timing of over-threshold signals. The hardware consists of a front-end amplification and discrimination(FEAD) board and an FPGA-based readout board. The FEAD converts detector signals into digital pulses, which are sent via USL connectors to the Field-Programmable Gate Array(FPGA). The FPGA measures the high-precision arrival time and uses a multi-phase pulse-width measurement to correct leading-edge time walk, while data are transferred to a PC (personal computer) through a Gigabit Ethernet link. Preliminary test results with a signal generator demonstrate synchronous readout of 32 channels with a time resolution better than 35 ps per channel and show an excellent linear response in pulse-width measurement. An upgraded FPGA board is under development, and further results will be presented in the meeting.

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Authors

Ms Qian He (Shandong University) Mr Hao Dong (Qufu Normal University) Mr Bo Wang (Shandong University) Ms Xiaohan Sun (Shandong University) Feng LI (USTC) Kun Hu (Shandong University (CN)) Ms Yuying Li (Shandong University)

Presentation materials

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