Speakers
Description
In particle physics experiments, the front-end detector needs to transfer a large volume of data while minimizing power consumption due to the high density of readout channels and limited cooling space. Compared to traditional current mode logic (CML) drivers, source series terminated (SST) drivers exhibit approximately 50% better power efficiency. This paper presents an SST transmitter that utilizes an edge-pre-emphasis method to maintain a high data transmission rate while minimizing power consumption. The proposed design consists of a phase-locked loop (PLL) for clock generation, a serializer for parallel data serialization, an SST driver for serial data output, and a serial peripheral interface (SPI) for configuration. The SST driver integrates a main driving stage to provide an output current of around 5 mA, a programmable pull-up and pull-down transistor array to adapt the output resistance, a programmable edge-pre-emphasis circuit to adjust the emphasis strength, and a programmable delay chain to modify the emphasis duration. The SST driver can achieve an 11-Gbps data rate. The simulated power consumption of the SST driver is typically 14 mA, with a maximum range of 5 to 21 mA, depending on the output resistance, emphasis strength and duration. It can reduce power consumption by a minimum of 44% compared to the CML driver from the previous version. The design, along with a separate test chip dedicated exclusively to the SST driver, has been fabricated using 55-nm CMOS technology. Laboratory tests are expected to begin in late February, and detailed design and measurement results will be presented.
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