25th IEEE Real Time Conference - La Biodola, Elba, Italy

A low jitter 2.56 Gbps reference-less CDR ASIC in 55 nm for NICA Multi-Purpose Detector Project

25 May 2026, 14:45

1h

Elena Room (Hotel Hermitage)

Poster presentation Front-End Electronics, Fast Digitizers, Fast Transfer Links & Networks Front-End Electronics, Fast Digitizers, Fast Transfer Links & Networks - PS

Speakers

Cong ZhaoProf. Di Guo (Central China Normal University)

Description

Nuclotron-based ion collider facility (NICA) is a new accelerator complex designed at the joint institute for nuclear research to study properties of dense baryonic matter. The multi-purpose detector (MPD) is one of three detectors in NICA. The bi-directional serial optical data transceiver system is employed between the front-end and the back-end in the detector readout electronics. The low jitter clock data recovery (CDR) ASIC is one of the key components in the high-speed serial down link direction. This paper presents the design and the test results of a low jitter 2.56 Gbps reference-less CDR ASIC for NICA MPD project. The CDR ASIC consists of an input equalizer stage, a bang-bang phase detector (BBPD), a charge pump circuit (CP), a low-pass filter (LPF), a LC voltage-controlled oscillator (LC-VCO) circuit and a SPI module.
The CDR ASIC has been fabricated in a 55 nm CMOS process. The phase noise test results show that the CDR ASIC outputs the 2.56 GHz clock with a phase noise of -110 dBc/Hz at 1 MHz offset and a rms jitter of 857 fs. The logic test results show that the recovered 2.56 Gbps data is correct and the BER less than 10−12 is achieved in all tests.