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Description
Waveform digitization directly samples detector analog signals and extracts timing and amplitude information via digital signal processing, and is widely used in readout electronics for nuclear and particle physics experiments. Switched Capacitor Array (SCA) architectures combine high-speed analog sampling with low-speed analog-to-digital converters (ADCs), offering advantages in power consumption, integration level, and achievable sampling rate compared with ultra-high-speed ADC-based solutions.
This work proposes a configurable waveform digitization architecture based on cascading multiple custom-developed developed SCA chips. For a two-chip configuration, the input signal is equally split by a wideband passive power divider and fed into two SCA chips. A phase-locked loop (PLL) controls the sampling clock phases, while FPGA-based trigger logic enables multiple operating modes. Time-interleaved sampling with a 180° phase offset achieves high sampling rates, waveform concatenation extends sampling depth, and alternating trigger allocation improves event rate.
Based on this concept, a multi-mode waveform digitization prototype was designed and implemented. Laboratory measurements demonstrate sampling rates of up to 10 Gsps, a continuous sampling window of approximately 100 ns, and an event processing capability of about 100 kHz. Further joint tests with a Picosecond Micromegas detector validate a 10 Gsps effective sampling rate and achieve a timing resolution better than 26 ps in cross-chip operation.
| Minioral | Yes |
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| IEEE Member | No |
| Are you a student? | Yes |