Speaker
Description
The Phase-2 upgrade of the CMS detector at the High-Luminosity LHC (HL-LHC) will increase the overall throughput of the detector readout from 1.6 Tbps of the present-day system to 51 Tbps. This increment in data rate corresponds to an increase in the Level-1 trigger rate from 100 kHz to 750 kHz during HL-LHC. The increase in the latency and trigger rate requirements of the Phase-2 Level-1 trigger system requires the CMS Electromagnetic Calorimeter (ECAL) to shift the buffering of detector data and the generation of trigger primitives from the ASIC-based front-end electronics to a more flexible FPGA-based backend. A DAQ readout scheme is implemented on the Barrel Calorimeter Processor (BCP) board, which is based on the Xilinx XCVU13P FPGA. The firmware implementation is highly flexible and allows buffering of ECAL data for up to 12.8 $\mu$s and handling trigger rates as high as every LHC bunch-crossing (40 MHz). The firmware also provides flexibility to select a range of readout windows from as low as one bunch-crossing to as high as 256 bunch-crossings. It also provides the ability to handle back-pressure emerging from any source in the CMS DAQ system. To improve efficiency and relax the overall CMS DAQ, it can reduce the size of every triggered event dynamically using the Zero-Suppression (ZS) scheme. The design is tested on the BCP board using CMS-simulated data as well as from the prototyped ECAL ASIC front end. The proposed design and the test performance are summarized in the poster.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |