Speaker
Description
As trigger and data acquisition system complexity grows, processing near the detectors becomes essential to cope with throughput and event selection requirements. In this context, real-time artificial intelligence (AI) is gaining momentum. While FPGAs with AI engines are available, they are limited by power consumption, area, and latency due to the von Neumann bottleneck. In-memory computing mitigates these limitations by co-locating data and processing. Using conductance-tunable analog computing elements enables power-efficient vector-by-matrix multiplications, outperforming complementary metal-oxide-semiconductor (CMOS) digital processing by orders of magnitude. However, programming the conductance requires digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), adding complexity and power overhead, and limiting scalability in purely digital integrated circuits.
This work is a pioneering exploration of memristive–CMOS hybrid electronics for experimental physics, covering conductance programming experiments for memristors and the development of all-digital DACs and ADCs for hybrid memristive–FPGA computing. Our bench-top measurements demonstrate that it is possible to tune the conductance of KnowM self-directed channel memristors over eight non-overlapping conductance states within a 50–250 μS range, with a 10% error. Our ADC has a Wilkinson architecture and incorporates a 400 MSps time-to-digital converter based on a tapped delay line with 3.5 ps elements. It operates with 6.2 effective number of bits (ENOB) at 1 MHz over a 1.5 V input range, and full-scale nonlinearity below 1%. Our DAC, based on a digitally controlled delay line, operates up to nearly 500 kHz with 7.9 ENOB, covering a 2.3 V output range.
| Minioral | No |
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| IEEE Member | Yes |
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