Speaker
Description
Machine learning (ML) inference on FPGAs has been widely adopted in real-time triggering of collider experiments for detector signature identification. The ML application in Front-End Electronics (FEE) has not yet been fully explored, primarily due to constraints such as limited FPGA resources and localized detector coverage.
In this work, we develop an ML-based waveform discrimination method for the Central Drift Chamber (CDC) of Belle II to reduce cross-talk noise at the front-end level. The Belle II CDC is a key charged-particle tracking detector for both offline and the real-time hardware trigger. During Belle II operation, background wire hits have been observed in the CDC FEE, where multiple hits occur in neighboring anode wires by large energy deposit. The hardware track trigger employs a Hough transformation based on track segments formed by combining hits from multiple wire layers. Due to the reduced dimension and the coarse mesh size in the conformal plane, the hardware track trigger is particularly sensitive to cross-talk noise, hence resulting in an increased fake trigger rate with higher luminosity in the future.
In our implementation in the FEE's Xilinx Virtex-5 FPGA, ML modules are operating in parallel on individual wire channels. Given its limited resources compared to modern devices, the primary challenges are not only achieving sufficient signal-noise discrimination, but also minimizing FPGA resource usage. We report on the ML model development, FPGA deployment, and validation with Belle II operation. The prospects for future Belle II upgrades incorporating this intelligent Front-End application will also be outlined.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | No |