25–29 May 2026
La Biodola - Isola d'Elba (Italy)
Europe/Rome timezone
NB: The submission deadline for the Student Paper Awards is Monday, 11 May.

Cost-effective and competitive alternative to the ITER Time Communication Network for accurate time synchronization

26 May 2026, 15:20
20m
Maria Luisa Room (Hotel Hermitage)

Maria Luisa Room

Hotel Hermitage

Oral presentation Data Acquisition and Trigger Architectures Front-End Electronics, Fast Digitizers, Fast Transfer Links & Networks

Speaker

Luca Trevisan (Consorzio RFX)

Description

In large-scale fusion experiments, such as those addressing the major energy challenges of the current century, accurate control and data acquisition systems are crucial for facility operation and the validation of fundamental theories. Diagnostic systems require integration strategies to manage the high data volume, ensure high sampling rates and precisely synchronize control actions. Since control equipment is geographically distributed, temporally accurate triggering is essential to coordinate data acquisitions across the experiment.
This coordination challenge is being addressed at the ITER Neutral Beam Test Facility, which hosts the MITICA experiment. Since MITICA is developing ITER's full-size injector, its control system strictly adheres to ITER CODAC directives. Synchronization is achieved via the Time Communication Network, based on the IEEE1588 v2 protocol. Using National Instruments PXI-6683H devices and proprietary APIs, a full TCN network was successfully implemented at the NBTF, achieving the required synchronization accuracy with an RMS of less than 50 ns
However, the cost of scaling this solution is substantial. The need of a dedicated server, a National Instruments chassis and a PXI-6683H module for each TCN node prompted the exploration of more economical and efficient alternatives.
To this end, we decided to develop a complete and cost-effective solution, based on FPGA technology. Leveraging the knowledge gained with the MITICA TCN and its PTP protocol, we propose a device utilizing a KRIA KR260 board and the Petalinux framework. This board can generate synchronized clock and trigger signals via PTP and is designed for simple and cost-effective integration into existing synchronization infrastructure.

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Author

Luca Trevisan (Consorzio RFX)

Co-authors

Mr Aamir Ali Patoli (DIMES) Andrea Rigoni Garola (RFX) Mr Gabriele Manduchi (RFX) Mr Mattia Bevilacqua (Università di Padova/Consorzio RFX) Roberto Cavazzana

Presentation materials

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