7–10 Oct 2025
Inn at Penn, University of Pennsylvania
US/Eastern timezone

Network intelligence for fault tolerance and data load balancing

8 Oct 2025, 18:30
1h 50m
Inn at Penn, University of Pennsylvania

Inn at Penn, University of Pennsylvania

3600 Sansom Street, Philadelphia, Pa 19104
Poster RDC 3 Solid State Tracking Poster

Speaker

Maurice Garcia-Sciveres (Lawrence Berkeley National Lab. (US))

Description

This project will use on-chip machine learning algorithms to produce intelligent networks. Both conventional digital logic and spike-based neuromorphic implementations will be explored. Two network scales will be prototyped: a multi-chip network, where each element is a complex functionality sensor and many sensors are integrated on a circuit board to form the network (suitable for DUNE or other detectors of similar scale), and a network-on-chip, where the individual pixels of a sensor are the network elements (suitable for collider pixel detectors). Both these cases are 2-dimensional, regular geometry networks, where each element has exactly 4 neighbors. A third case, corresponding to an ad-hoc wireless network in 3-dimensional space, relevant for proposed smart dust detector systems, will be investigated with theory and simulation.

Author

Maurice Garcia-Sciveres (Lawrence Berkeley National Lab. (US))

Presentation materials

There are no materials yet.