The author has developed a clock distribution system for front-end electronics synchronization using the clock-duty-cycle-modulation (CDCM) [1] based transceiver (CBT), which is realized by the Xilinx Kintex-7 IOSERDES primitives. In addition, the link layer protocol called the MIKUMARI link was developed. The link protocol can transfer not only data using frame structure but also a one-shot...
To increase the science rate for high data rates (100Gbs - 1Tbs) with guaranteed Quality of Service (QoS), JLab is partnering with ESnet for proof-of-concept engineering of an 1.5 network layer AI/ML directed dynamic Compute Work Load Balancer (CWLB) of UDP streamed data using an FPGA for fixed latency and high throughput in order to demonstrate seamless integration of edge / core computing...
