Conveners
RDC 4 Readout & ASICs
- Mitchell Franck Newcomer (University of Pennsylvania (US))
- Lorenzo Rota (SLAC National Laboratory)
RDC 4 Readout & ASICs
- Lorenzo Rota (SLAC National Laboratory)
- Mitchell Franck Newcomer (University of Pennsylvania (US))
RDC 4 Readout & ASICs
- Lorenzo Rota (SLAC National Laboratory)
- Mitchell Franck Newcomer (University of Pennsylvania (US))
-
Adrian Nikolica (University of Pennsylvania (US))07/10/2025, 16:30RDC 4 Readout & ASICsParallel session talk
Efficient power conversion and distribution is an important consideration for advanced detectors as power requirements and channel density increase. Future detectors will have unique requirements such as very low mass, and ability to operate in environments with high magnetic fields or radiation. Switched power converters using inductive elements are difficult to miniaturize, generate...
Go to contribution page -
Danny Noonan (Fermilab), Danny Noonan (Fermi National Accelerator Lab. (US)), Danny Noonan (Fermilab)07/10/2025, 16:50RDC 4 Readout & ASICsParallel session talk
The CMS experiment’s High Granularity Calorimeter (HGCAL) upgrade will replace CMS’s existing endcap calorimeters in preparation for the High Luminosity LHC. To effectively use over 6 million channels of this “imaging” calorimeter, CMS has developed two novel Endcap Concentrator (ECON) ASICs to perform data compression/selection on detector. The ECON-D ASIC operates on the 750kHz data path,...
Go to contribution page -
Paul Keener (University of Pennsylvania (US))07/10/2025, 17:10RDC 4 Readout & ASICsParallel session talk
With ASICs becoming more complex and traditional verification frameworks, such as UVM, requiring specialized knowledge, alternatives such at the cocotb python-based frameworks become attractive. In an academic environment, students who are already familiar with python can quickly be leveraged to write testbenches for complex ASICs. This talk will give a brief introduction to cocotb using our...
Go to contribution page -
Dr Sebastian White (University of Virginia (US))07/10/2025, 17:30RDC 4 Readout & ASICsParallel session talk
In preparation for HL-LHC operation, a number of new detector systems are being constructed with timing precision on physics objects of ≤50 picoseconds. These time stamps will reduce the level of pileup induced backgrounds as the number of interactions per crossing will reach of order 100-200.
Go to contribution page
In this report we note that this high pileup level will necessitate a new approach to calibration of... -
Adrian Nikolica (University of Pennsylvania (US))09/10/2025, 11:00RDC 4 Readout & ASICsParallel session talk
Waveform digitization remains the baseline method for reading out large scale neutrino detectors consisting of thousands of channels of photomultiplier tubes (PMTs). Because events in these detectors happen relatively infrequently, this method results is high cost, high power, and extremely high data volumes. The problems are compounded when considering that modern PMTs with very fast...
Go to contribution page -
Dr Gianluigi De Geronimo (University of Michigan, Stony Brook University, dgcircuits.com)09/10/2025, 11:20RDC 4 Readout & ASICsParallel session talk
The JLab SoLID experiment is assessing the VMM ASIC family for GEM tracker readout in high-rate environments. The current VMM3a falls short of requirements. We propose a VMM3b revision with optimized gain and shaping time for high-rate GEM and uRWell operation. Additionally, we are considering a VMM4 version, migrating to TSMC 65nm, with redesigned ADCs, digital core, and new features to serve...
Go to contribution page -
Danush Shekar (University of Illinois Chicago (US))09/10/2025, 11:40RDC 4 Readout & ASICsParallel session talk
Fine-granularity trackers have the potential to enhance high-priority physics in challenging environments of future high-energy experiments. This requires intelligent ways to overcome the strict bandwidth and power constraints of the detector. As part of the Smartpixels project, we have been developing and testing radiation-hard ASICs fabricated using a 28 nm CMOS process with on-chip neural...
Go to contribution page -
Prashansa Mukim (Brookhaven National Laboratory)09/10/2025, 12:00RDC 4 Readout & ASICsParallel session talk
The explosive growth in data rates being seen by next-generation detectors calls for transformative solutions that integrate intelligence at the edge. In this talk, we will present a smart readout application specific integrated circuit (ASIC) that incorporates advanced digital signal processing (DSP) and artificial neural networks (ANNs) directly into the detector front-end. By leveraging...
Go to contribution page -
Brooke Russell (Massachusetts Institute of Technology)09/10/2025, 16:30RDC 4 Readout & ASICsParallel session talk
LArPix is an end-to-end pixelated charge readout system for 3D imaging at the millimeter-scale in multi-tonne liquid argon time-projection chambers (LArTPCs). Leveraging large-scale commercial fabrication techniques, the system is designed to be highly scalable and robust, enabling low-cost quick-turn system production at industry standard. The system is based on the LArPix ASIC, a...
Go to contribution page -
Bojan Markovic09/10/2025, 16:48RDC 4 Readout & ASICsParallel session talk
Light readout systems with single-photon resolution are essential for next-generation HEP experiments, including dark matter searches, neutrino detectors, and noble liquid experiments. Technologies such as silicon photomultipliers (SiPMs) and photomultiplier tubes (PMTs) offer low noise and scalability, making them well-suited for large-area detector arrays.
This work presents a cryogenic...
Go to contribution page -
Liang Yang (UC San Diego)09/10/2025, 17:06RDC 4 Readout & ASICsParallel session talk
Integrating cryogenic readout electronics directly into large noble liquid detectors offers reduced front-end noise and minimized detector backgrounds, thus enhancing sensitivity for rare event searches. The CRYO ASIC is a compact 7 mm × 9 mm System-on-Chip (SoC) waveform digitizer and serializer specifically designed for cryogenic operation. The ASIC interfaces directly with signals from time...
Go to contribution page -
Faith Beall (The University of Texas at Arlington)09/10/2025, 17:24RDC 4 Readout & ASICsParallel session talk
We present a Berkeley Short-channel IGFET Model (BSIM4)-based cryogenic Process Design Kit (PDK) for the open-source Skywater 130nm transistor node for operation at 77 Kelvin. Reliable operation of read-out electronics at cryogenic temperatures is crucial for their use in liquid argon detectors that are ubiquitous in high energy physics (HEP) experiments. The open-source Skywater 130nm node is...
Go to contribution page -
Brian Lenardo09/10/2025, 17:42RDC 4 Readout & ASICsParallel session talk
Advances in high-energy physics (HEP) increasingly rely on ASICs operating at cryogenic temperatures. While modern 28 nm CMOS offers superior speed, power efficiency, and integration density, its behavior under deep cryogenic conditions deviates significantly from nominal operation. Threshold voltage shifts, mobility enhancement, mismatch, noise, and reliability mechanisms all change...
Go to contribution page