7–10 Oct 2025
Inn at Penn, University of Pennsylvania
US/Eastern timezone

Q-Pix: Pixelated Charge Readout Design, Prototyping, & Simulation

9 Oct 2025, 17:00
15m
Inn at Penn, University of Pennsylvania

Inn at Penn, University of Pennsylvania

3600 Sansom Street, Philadelphia, Pa 19104
Parallel session talk RDC 4 Readout & ASICs RDC 4 Readout & ASICs

Speaker

Kalindi Gosine (University of Texas at Arlington)

Description

Future long baseline neutrino experiments such as the Deep Underground Neutrino Experiment (DUNE) call for the deployment of multiple multi-kiloton scale liquid argon time projection chambers (LArTPCs). Traditional wire-plane technologies present a set of challenges in the construction of the anode planes, the continuous readout of the system required to accomplish the physics goals of proton decay searches and supernova neutrino sensitivity, and the 2D projective reconstruction of complex neutrino topologies.
The Q-Pix concept (arXiv: 1809.10213) is a continuously integrating low-power charge-sensitive amplifier (CSA) viewed by a comparator. When the trigger threshold is met on a clock edge, the comparator initiates a ‘reset’ transition and returns the CSA circuitry to a stable baseline. This is the elementary Charge-Integrate / Reset (CIR) circuit. The instance of reset time is captured in a 32-bit clock value register, buffers the cycle and then begins again. What is exploited in this new architecture is the time difference between one clock capture and the next sequential capture, called the Reset Time Difference (RTD). The RTD measures the time to integrate a predefined integrated quantum of charge (Q). Waveforms are reconstructed without differentiation and an event is characterized by the sequence of RTDs. This technique easily distinguishes the background RTDs due to 39Ar decays (which also provide an automatic absolute charge calibration) and signal RTD sequences due to ionizing tracks. Q-Pix offers the ability to extract all track information providing very detailed track profiles and also utilizes a dynamically established network for DAQ for exceptional resilience against single point failures.
This talk will present the status of the charge readout design, introduce results from the first ASIC prototype and simulation, and discuss future planned tests.

Author

Kalindi Gosine (University of Texas at Arlington)

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