Speaker
Description
The pFREYA16, prototype Fast Readout for ptYchography Applications with 16 channels, ASIC is a pixellated 8-by-2 readout matrix developed for ptychography experiments based on fourth generation storage ring light sources, also known as Diffraction-Limited Storage Rings (DLSR), pushing towards continuous wave operation. The target of the experiment is to obtain a 128-by-128 matrix of pixels, working at a frame rate of 1 MHz with single-photon resolution, as well as low-noise and low-power figures, in a modest-size pixel area of 150 μm x 150 μm. The current prototype reports respectively a noise of 250 e$^{-}$ rms and a power consumption of 220 μW per pixel. The readout chain is composed of a switch-reset CSA and a semi-Gaussian unipolar RC-CR shaper, and includes signal discrimination, zero-suppression capabilities, and pixel-level analog to digital conversion. The ASIC is also configurable for 5, 9, or 25 keV input photon energy, with a full well of 256 equivalent photons in each mode, and four different peaking times are available for noise optimisation. The conference presentation will focus on a full characterisation of the CSA and the shaper stage, and will provide insight into the equivalent noise charge obtained in each mode, with a comparison between post-layout simulations and actual measurements on the chip.
