20–23 Oct 2026
University of Washington
America/Los_Angeles timezone

ALICE ITS3 MOSAIX sensor measurements and developments for ePIC SVT

22 Oct 2026, 10:50
15m
Auditorium (Alder Hall)

Auditorium

Alder Hall

Presentation RDC 3 Solid State Tracking Plenary

Speaker

Gregor Hieronymus Eberwein (Massachusetts Inst. of Technology (US))

Description

The ALICE Inner Tracking System (ITS3) upgrade introduces the first vertex detector based on wafer-scale, reticle-stitched, bent Monolithic Active Pixel Sensors (MAPS). The concept is being adopted for the Silicon Vertex Tracker (SVT) of the future ePIC detector at the Brookhaven National Laboratory (BNL) based Electron Ion Collider (EIC). The MOnolithic Stitched Active pIXel sensor (MOSAIX), developed in TPSCo 65 nm CMOS imaging technology, comprises twelve Repeated Sensor Units along a 1D-stitched die, completed by a Left Endcap (LEC) and Right Endcap (REC) for data readout and powering. The LEC embeds on-chip eight high-speed serializers operating at 5.12 and 10.24 Gbps. The SVT will require a large-scale production and testing of MOSAIX-based sensors on approximately 400 wafers.

On-wafer yield characterisation with full validation of the multi-Gbps data links is the ideal approach to select sensor planes for thinning and dicing used for final ITS3 detector construction. It is essential for the high-throughput high-volume SVT production QC.

After an introduction to both ITS3 and SVT detectors, this contribution focuses on the development and results of the high-speed wafer-level testing approach: The use of vertical probe needles rather than commonly used cantilever probe cards allows for multi-Gbps readout (needle inductance reduced by approx. one order of magnitude) when combined with a custom high-speed interconnect chain. The goal of the developed test system and framework is to enable full chip characterisation and QC on-wafer without the need for destructive on-carrier PCB testing, requiring glueing and wirebonding of diced dies. Wafer-probing of single wafer-scale sensors thinned to 50~$\mu$m is demonstrated.

Characterisation and yield results of O(40) tested wafers will be presented: Powering, slow-control, biasing, on-chip data transmission, and pixel matrix performance are evaluated. The high-speed readout performance is assessed via dedicated Bit-Error-Rate and eye-diagram measurements. Results from this testing campaign inform design choices for the final production run of the MOSAIX sensor for ITS3, and highlight on-wafer high-speed QC required for future detector systems relying on large-area, high-bandwidth MAPS instrumentation.

Author

Gregor Hieronymus Eberwein (Massachusetts Inst. of Technology (US))

Presentation materials