Description
We present new methods for efficiently implementing quantum low-density parity-check (qLDPC) codes on hardware-constrained two-dimensional architectures. Our focus is on square-lattice devices with nearest-neighbour connectivity, motivated by physically realistic superconducting and silicon-based quantum processors. While qLDPC codes promise improved asymptotic performance compared with surface codes, their practical implementation is limited by non-local stabiliser measurements and the routing overhead required on geometrically local hardware. We address this problem by developing qubit allocation, routing, and swapping strategies, as well as novel scheduling strategies that map qLDPC syndrome-extraction circuits onto realistic lattice layouts.
We study both deterministic constructions and heuristic optimisation methods for the underlying swapping problem, aiming to reduce circuit depth, congestion, and the number of additional operations required for stabiliser measurement. These methods allow us to directly compare the established surface-code architectures with leading qLDPC candidates, including promising bivariate bicycle codes such as the Gross code, under comparable physical-resource and connectivity constraints. Our results indicate that, even under strict nearest-neighbour constraints, carefully optimised scheduling can significantly reduce the overhead associated with qLDPC syndrome extraction and can reveal regimes where qLDPC codes provide a practical, circuit-level advantage over surface-code-based approaches.
We further investigate extensions beyond the square lattice. In near-future architectures with limited long-distance connectivity, we find substantially improved routing performance, suggesting that even modest hardware enhancements can unlock more of the potential of qLDPC codes. We also consider triangular and other alternative lattice connectivity, where the increased local coordination enables more efficient scheduling and further reductions in circuit overhead. Overall, our work provides a hardware-aware pathway toward implementing qLDPC codes on realistic near-term quantum devices and clarifies the architectural features most relevant for achieving a practical advantage over surface codes.
| I am the presenting author | No |
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| If you are not the presenting author, please give the presenting author's name: | Zsolt Szabó |