Speaker
Description
Vertex detectors for future experiments, e.g., at a possible FCC-ee, will require an unprecedented spatial resolution below 3 µm, a time resolution in the order of 5 ns, a hit-rate capability approaching 100 MHz/cm², and an extremely low material budget only achievable by sensors thinned to 50 µm, and limiting the power consumption below 50 mW/cm².
The OCTOPUS project aims to develop a Monolithic Active Pixel Sensor (MAPS) to meet all these requirements in a staged approach, currently targeting a 65nm CMOS imaging process. The project combines TCAD and Allpix Squared simulations, ASIC development, data acquisition, and beam-test characterization within a common design framework.
An intermediate objective is the realization of a high-resolution MAPS sensor with relaxed timing and power constraints for beam telescope applications for detector characterization at test beams.
Current R&D activities focus on optimized sensor layouts, including the NCross concept to improve charge sharing at pixel pitches of around 20 µm. In parallel, dedicated ASIC architectures are under development, featuring compact low-power in-pixel front-ends, asynchronous matrix readout based on Asynchronous Priority Arbiter (APA) schemes, and end-of-column time stamping with 5 ns precision. The project will also assess and evaluate technology prototypes, including a proof-of-concept demonstrator for an APA-based readout architecture.
This contribution presents the current status and plans for OCTOPUS, including simulation results for sensor design optimization, the design of a first prototype ASIC, and evaluation results from demonstrators using the Caribou DAQ system.