Speaker
Description
Real-time jet classification in high-energy physics requires high predictive performance under strict latency, throughput, and FPGA-resource constraints. Although aggressive weight quantisation promises simpler arithmetic, reductions in numerical precision and theoretical operation count do not necessarily translate into more efficient synthesised implementations. This study investigates whether the predictive gains of BitNet-style binary- and ternary-weight neural networks survive FPGA synthesis.
The benchmark uses the public OpenML hls4ml_lhc_jets_hlf dataset, consisting of approximately 830,000 jets described by 16 high-level observables and balanced across gluon, light-quark, W, Z, and top classes. The primary task separates light-flavour QCD-like quark and gluon jets from jets labelled as W, Z, or top. Using fixed stratified data partitions and three training seeds, the study compares dense, fixed-point QKeras, HGQ, binary and ternary QKeras, BitNet binary, and BitNet-1.58 networks using two multilayer-perceptron architectures matched across model families. An unrolled XGBoost boosted decision-tree ensemble provides a tree-based reference. Neural networks are synthesised with hls4ml and decision trees with Conifer, targeting a Xilinx VU13P FPGA with a 5 ns clock period and initiation interval II=1.
BitNet-style learned scaling consistently improves predictive performance over the corresponding binary and ternary QKeras models, with BitNet-1.58 providing the strongest performance among the tested ultra-low-bit neural networks. However, these predictive gains do not automatically produce the most efficient FPGA implementations, as the learned scaling introduces implementation-dependent overhead. Seven-bit QKeras, meanwhile, matches the dense floating-point baseline in predictive performance while reducing latency, LUT usage, and DSP usage. Among the tested implementations, HGQ provides the strongest neural resource-efficiency trade-off, and the unrolled boosted decision-tree ensemble achieves the lowest synthesised latency.
The results demonstrate that nominal numerical precision alone is insufficient to predict FPGA efficiency. Scaling-factor realisation, structural sparsity, compiler scheduling, and model-conversion pathways can determine whether the apparent benefits of ultra-low-bit inference survive synthesis. The reported results are based on HLS C-synthesis estimates and provide a foundation for subsequent place-and-route validation.