7–10 Oct 2025
Inn at Penn, University of Pennsylvania
US/Eastern timezone

FPGA-acceleration of image feature extraction for the ATLAS experiment at CERN at the Large Hadron Collider

8 Oct 2025, 18:30
1h 50m
Inn at Penn, University of Pennsylvania

Inn at Penn, University of Pennsylvania

3600 Sansom Street, Philadelphia, Pa 19104
Poster RDC 5 Trigger & DAQ Poster

Speaker

Tong Xu (Argonne National Laboratory (US))

Description

Fast and efficient processing of data from the tracking detector of the ATLAS experiment is required for the high-luminosity program. The tracking detector is equipped with semiconductor sensors with high-segmentation of about 50 by 50 microns. A charged particle crossing a sensor ionizes a few pixels along its trajectory. Our firmware processes images from the sensors to calculate coordinates of particle crossings. The firmware groups pixels with non-negligible ionization into clusters and then estimates coordinates of the particle crossing by calculating cluster’s centroid. The firmware is programmed into FPGAs that run as CPU co-processors. The FPGAs will receive collision data from the experiment at the rate of about 1 MHz. We benchmark the performance of the clustering firmware interfaces at Vitis kernel and compare it to a clustering algorithm for CPUs. The FPGAs in AMD Alveo U250 cards demonstrate faster processing and energy savings in comparison to the CPUs.

Author

Tong Xu (Argonne National Laboratory (US))

Presentation materials

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