Speaker
Description
A cosmic muon veto detector is being built around the RPC detector which is operational at TIFR, Mumbai. It will study the feasibility of building a shallow depth neutrino detector. It’s being built using extruded plastic scintillator (EPS) strips. Muon interactions in the EPS are detected by SiPMs mounted at the end of 2 wavelength shifting fibres which are inserted in the EPS strips.
The muon detection efficiency of the CMVD is required to be more than 99.99%. Faithful detection of muons requires SiPM charge measurement. SiPM signals are converted to voltage pulses by trans-impedance amplifiers. A DRS4 based readout system is being designed to sample the signals at a rate of 1 GSa/s. The samples are digitised on receiving a mini-ICAL trigger, and zero suppressed data are transmitted to the back-end data server. The data acquisition is controlled by an AMD Spartan-7 FPGA. A soft-core processor (microblaze) is instantiated inside the FPGA to carry out the DAQ process control. An FPGA based DAQ board consisting of 5 DRS4 ASICs and a network interface is being designed. This paper will discuss the prototype design of the SiPM readout board using the DRS4 ASIC and the Spartan-7 FPGA.
| Field of contribution | Experiment |
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