Speaker
Description
The ePIC Silicon Vertex and Tracking (SVT) detector will be constructed with large-area Monolithic Active Pixel Sensors (MAPS), called EIC-LAS. Serial powering will be used for the two outermost barrel layers and the disks (in both hadron and electron directions), utilising Shunt Low-Dropout (SLDO) regulators. This powering scheme achieves a minimized material budget; combining shunting of excess current and low-dropout power supply voltage regulation and enables multiple voltage regulators per EIC-LAS. However, it also introduces several challenges; such as, the floating “ground” nodes of each EIC-LAS requiring generation of local negative sensor back-biases. Unlike the ATLAS ITk scheme, it is not possible to bring a common high voltage directly from outside due to the high precision of this bias voltage required by MAPS-based detectors. Additionally, to reduce resources, slow controls should be consolidated into a single lpGBT e-link. Therefore, a team consisting of ASIC designers from RAL (UK), BNL (US) and LBL (US) has been developing an ASIC, called Ancillary ASIC (AncASIC), to provide power, bias, slow control and operational management for the EIC-LAS within the ePIC SVT detector. AncASIC comprises SLDOs for multi-domain power supply, a Negative Voltage Bias Generator (NVBG) for sensor back-biasing, and slow-control management for both the AncASIC itself and for EIC-LAS operations. So far, two test ASICs have been developed and fabricated in a multi-project wafer (MPW) run from March 2025 to validate the NVBG and SLDO functionalities separately. Test results of these prototypes will be presented in detail. Characterizations of voltage regulation, load capability, transient response, noise, and operational stability, including exposure to ionizing irradiation doses, were performed and will be discussed. Recently, an advanced test article, combining most of the ultimate functionalities, including multiple SLDOs, increased current output NVBG, monitoring ADC, temperature measurements, and internal AncASIC control block, was designed and submitted for fabrication in an MPW run (September 2026). The AncASIC test articles were implemented in a specialized 110-nm Partially-Depleted Silicon-on-Insulator (PD-SoI) technology that can handle positive and negative voltages. The design features of this new ASIC will also be presented.