Speaker
Description
Designing networks of communicating digital nodes requires connecting system-level behavior to the RTL from which hardware will be produced. RTLswarm is a parallel, distributed, cycle-accurate simulator that incorporates Verilator-generated C++ RTL models into independently executing node processes coordinated through a messaging network. Software-defined scenarios, tracing, and analysis allow network-scale outcomes to be related to specific internal RTL behavior. This organization supports a short question–experiment–diagnosis–redesign loop as the RTL evolves, while the same simulator can provide repeatable system-level verification after the design stabilizes. We demonstrate RTLswarm using an existing digital-core RTL design in a multi-chip network and characterize its synchronization and throughput across multiple network sizes. The results show that RTLswarm sustains hundreds of synchronized clock ticks per second while preserving cycle-level behavior. RTLswarm therefore complements block-level verification and downstream implementation checks by providing a common environment for RTL design iteration, network-level diagnosis, and system verification.