Speaker
Description
Current generation pixel detector readout chips are prone to data congestion and local failures that can cause a larger-scale loss of channels or event data. On-chip intelligent networks between groups of pixels could forego these issues by avoiding single-point-of-failures and dynamic routing around congestion or failed network nodes. We developed a simulation framework to understand key aspects of these networks and determine the best topology, routing algorithm, and other aspects arising from using an on-chip network. For the 4D Fabric project, a readout chip has been simulated with the same geometry as the ITkPix readout chip for the upgrade of the ATLAS detector tracker for the HL-LHC. This will serve to develop a baseline for an on-chip network to be used for the development of a scalable Pixel detector readout chip digital architecture to be used for 4D Pixel detectors at future collider experiments.